A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

Abstract

This paper presents a low-jitter, low-power and a small-area injection-locked all-digital PLL (IL-ADPLL). It con- sists of a dual-loop and a dual-VCO architecture in which one VCO (Replica) is placed in a TDC-less synthesizable ADFLL to provide continuous tracking of voltage and temperature variations. The other VCO (main) shares the control voltage with the replica VCO but is placed outside the loop and i s injection-locked to lower its jitter and accurately set its fr equency to the desired one. Thi s approach avoids timing problems in the conventional ILPLL since the injection-locked VCO is placed outside the feedback loop. It also achieves a low power and a small area, due to the abs ence of a power hungry TDC and an area-consuming loop filter, while tracking any PVT variations. The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show t hat it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of –243 dB. It al so consumes an area of only 0.022 mm² resulting in the best performance-area trade-off system presented up-to-date.