JSSC 2014第1期Clocking & PLLs

A V ersatile Timing Microsystem Based on Wafer-Level Packaged XTAL/BAW Resonators With Sub- W RTC Mode and Programmable HF Clocks David Rufﬁeux, Nicola Scolari, Frédéric Giroud, Thanh-Chau Le, Silvio Dalla Piazza, Felix Staub, Kai Zoschke, Charles-Alix Manier, Hermann Oppermann, To mmi Suni, James Dekker, and

提出基于晶圆级封装XTALBAW谐振器的微型计时系统，实现高集成度与小尺寸

0.4W功耗/2ppm稳定性（-40℃~85℃）/1.5×1.1×0.7mm³尺寸

石英晶体谐振器硅中介层晶圆级封装实时时钟可编程时钟

▸创新点1：晶圆级真空封装技术（方法创新） - 该论文提出了一种新型的晶圆级真空封装技术，用于封装调谐叉石英晶体(XTAL)，通过真空环境显著提升了谐振器的Q值和频率稳定性，实现了高成品率和小型化(1.5×1.1×0.7 mm)。

▸创新点2：硅中介层TSV集成（系统创新） - 采用硅中介层与TSV(Through-Silicon Via)技术集成，实现了谐振器与ASIC的单片化集成，为时序微系统的微型化和高完整性提供了关键技术支撑。

▸创新点3：可编程时钟输出（1-50MHz）（电路创新） - 通过RC PLL或2GHz BAW DCO分频技术，实现了1-50MHz范围内可编程时钟输出，功耗分别为100μW和5.3mW，提供了灵活的时钟解决方案。

▸创新点4：低功耗高稳定性设计（系统创新） - 在RTC模式下实现了0.4μW的超低功耗和±2ppm的频率稳定性（-40°C至85°C），显著提升了系统能效和环境适应性。

Abstract

This paper introduces and demonstrates with high yield a novel concept for the packaging under vacuum of tuning fork quartz XTALs on top of a silicon interposer equipped with TSVs. It paves the way to the implementation of a monolithic timing microsystem where the ASIC is part of the housing of a newly designed tiny 131-kHz XTAL to reach extreme module miniaturization (1.5 1.1 0.7 mm ) and integrity. As this task is still ongoing, an early demons tration of the generic versatile timing module is presented using a chip-on-board approach with standalone conventionally packaged XTAL and BA W resonators. The module achieves 0.4 W power dissipation and 2p p m stability over 40 Ct o8 5 C in RTC mode and can deliver on-demand programmable clocks between 1–50 MHz. The latter are obtained either with a RC PLL or after division of the signal obtained from a 2-GHz BA W DCO at a power dissipation of 100 W and 5.3 mW, respectively.