An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at 0VA c h i e v i n gZ e r oL e a k a g eW i t h 400-ns Wakeup Time for ULP Applications

Abstract

This paper presents a nonvolatile logic (NVL)-based 32-b microcontroller system-o n-chip (SoC) that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400 ns to re- store the system state upon po wer-up. Nonvolatile Fe-Cap-based mini-arrays backup the machine state and allow the chip to wake up instantly after a power cycle. Without NVL, a chip would either have to keep all flip-flops powered, resulting in high standby power, or waste energy and time rebooting after power-up. NVL allows systems to use leakier processes to achieve higher per- formance/lower dynam ic power while still having zero leakage in the sleep mode. Optimized system, architecture, and circuit techniques are presented that make NVL practical by adding only 3.6% to the SoC are a. Since nonvolatile elements are added to the SoC, reliability and testability have to be key features of the d e s i g n .T h i si st h efirst NVL SoC with measured NVL bitcell read signal margin d ata and extensive test and debug capabilities. The chip is fabricated in a commercial 130-nm low-leakage process and uses a single 1.5-V power supply.