Abstract
This work describes the circuit and physical design implementation of the processor chip (CP), level-4 cache chip (SC), and the multi-chip module at the heart of the EC12 system. The chips were implemented in IBM’s h igh-performance 32nm high-k/ metal-gate SOI technology. The CP chip contains 6 super-scalar, out-of-order processor cores, running at 5.5 GHz, while the SC chip contains 192 MB of eDRAM cache. Six CP chips and two SC chips are mounted on a high-per formance glass-ceramic sub- strate, which provides high-bandwidth, low-latency interconnec- tions. Various aspects of the design are explored in detail, with most of the focus on the CP chip, including the circuit design implemen- tation, clocking, thermal modeling, reliability, frequency tuning, and comparison to the previous design in 45nm technology.