The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server Ryuji Kan, Tomohiro Tanaka, Go Sugizaki, Kinya Ishizaka, Ryuichi Nishiyama , Sota Sakabayashi, Y oichi Koyanagi, Ryuji Iwatsuki, Kazumi Hayasaka, Taiki Uemura, Gaku Ito, Y oshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, and

Abstract

A 10th generation SPARC64 processor, fabricated in enhanced 28 nm CMOS, runs at 3.0 GHz and contains 16 cores with 24 MB shared L2 cache and system/DDR3/PCIe interfaces in 588 mm² die area. Using H-tree clock distribution network with shield wires, the average clock skew is minimized to 20 ps. Two-step read structure of GPR enables out-of-order execution across reg- ister windows. A large SMP system of up to 64 CPUs with ccNUMA uses a newly developed 14.5 GB/s SerDes. Column separation, al- ternate placement of master and slave latches and well slits are used to mitigate soft errors especially for multi-bit upsets. SER re- duction is observed by neutron irradiation experiments.