A7 2d BD R ,C T ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW John G. Kauffman , Member , IEEE

Abstract

This paper presents a single loop, third order contin- uous time ΔΣ modulator with an internal 4 bit qu antizer sampled at 500 MHz with only an oversampling ratio of 10. Since multi-bit operation commonly suffers from DAC non-linearities, and dy- namic element matching is ineffective at lo w oversampling, an al- ternative auxiliary DAC linearization is proposed for ΔΣ modula- tors. The unit element mismatches are digitally estimated based on a cross correlation of a binary test signal with the modulator output and represent the measured D NL of DAC1. The corresponding INL is calculated and stored in an 15×8 lookup-table which is ap- plied to the 8 bit auxiliary DAC to l inearize DAC1. Moreover, a de- sign centering approach for ampli fier finite gain bandwidth com- pensation within the loop filter is presented which allows for large bandwidth mismatch with neglig ible effect on loop filter stability. This results in a robust architecture over temperature, supply, and excess loop delay variations. The presented ΔΣ modulator achieves an SNDR of 67.5 dB, DR of 72 dB , and SFDR of 79 dB over a 25 MHz bandwidth and is implemented in a 1.2 V , 90 nm CMOS process. The modulat or occupies an active area of 0.19 mm² and has a power consumption o f8 . 5m W .I ta c h i e v e safigure of merit of 88 fJ/conv-step which is one of the best published for multi-bit ΔΣ modulators.