A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity Y uichi Miyahara, Mitsuhiro Sano, Kazuo Koya ma, Toshikazu Suzuki

Abstract

Opamp gain and nonlinearity are adaptively can- celled in a pipelined ADC that feat ures global zero-forcing LMS feedback. Two unique circuit concepts are incorporated into the design. One is a programmable gain element that adjusts the opamp gain and nonlinearity error, and the other is a digitally im - plemented oversampling quantizer that detects the error polarity with high precision. The total opamp-induced error is removed using an opamp input error monitoring algorithm, which also eliminates the opamp noise and offset. The proposed nonlin- earity-cancelled bottom-plate sampling helps to realize accurate inter-stage residue transfer and to alleviate the stringen tr e q u i r e - ment in the design of high-gain wideband opamps. A 60 MS/s pipelined ADC is prototyped in 0.18 µm CMOS. The chip exhibits a 14b INL with a 91 dB SFDR at 1.6 V using a plain un-casc oded two-stage opamp.