A 32 b 90 nm Processor Implementing Panoptic DVS Achieving Energy Ef ficient Operation From Sub-Threshold to High Performance Kyle Craig, Y ousef Shakhsheer, Saad Arrabi, Sudhanshu Khanna

Abstract

This paper presents a 32 b, 90 nm data flow processor capable of executing arbitrary DSP algorithms using fine graine d Dynamic Voltage Scaling (DVS) at the component level with rapid switching and dithering for near-ideal quadratic dynamic energy scaling from 0.25 V–1.2 V. This is the first full processor with Panoptic (all-in clusive) DVS, single clock cycle switching, dithering, and the ability to switch between high performance DVS operation and a sub-threshold m ode of operation. This paper also explores header switching and voltage selection considerations f or additional savings. Measure- ments show up to 80% and 43% energy savings of using P DVS over single ( )a n dm u l t i - ( ), respectively. Additionally, PDVS shows area savings of up to 65% over given the same energy consumption.