External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4–4 MHz Range

Abstract

This paper presents design techniques for a high power supply rejection (PSR) low drop-out (LDO) regulator. A bulky external capacitor is avoided to make the LDO suitable for system-on-chip (SoC) applic ations while maintaining the capability to reduce high-freque ncy supply noise. The paths of the power supply noise to the LDO output are analyzed, and a power supply noise cancellation circuit is developed. The PSR performance is impr oved by using a replica circuit that tracks the main supply noise under proces s-voltage-temperature varia- tions and all operating conditions. The effectiveness of the PSR enhancement technique is experimentally veri fied with an LDO that was fabricated in a 0.18 µm CMOS technology with a power supply of 1.8 V. The active core chip area is 0.14 mm², and the entire proposed LDO consumes 80 µ A of quiescent current during operation mode and 55 µA of quiescent current in standby mode. It has a drop-out voltage of 200 mV when delivering 50 mA to the load. The measured PSR is better than –56 dB up to 4 MHz when delivering a current of 50 mA. Compared to a conventional uncompensated LDO, the proposed architecture presents a PSR improvement of 34 dB and 25 dB at 1 MHz and 4 MHz, respec- tively.