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Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold
提出间歇谐振时钟技术，可在任意时钟频率下降低功耗。
0.37V 32位加法器阵列，时钟功耗降低36%，泄漏功耗降低81%
间歇谐振时钟低功耗亚阈值逻辑时钟频率CMOS
▸创新点1：间歇谐振时钟技术（IRC）是一种方法创新，通过间歇性地激活谐振时钟，显著降低了时钟功耗，突破了传统谐振时钟只能在窄频率范围内工作的限制。
▸创新点2：IRC适用于近/亚阈值逻辑电路，这是一种电路创新，能够在低电压（0.37 V）环境下有效工作，扩展了谐振时钟技术的应用场景。
▸创新点3：IRC实现了灵活选择时钟频率的系统创新，能够在任何时钟频率下降低功耗，测量结果显示在980 kHz时时钟功耗降低了36%。
▸创新点4：IRC显著降低了时钟泄漏功耗，测量结果显示泄漏功耗降低了81%，这是电路创新的重要贡献，特别适用于低功耗设计。
Abstract
In order to eliminate the limitation of a narrow frequency range of conventiona l resonant clocking, intermittent resonant clocking (IRC) is proposed for near/sub-threshold logic circuits. In this paper, IRC is applied to 0.37 V 32-bit adder array with latches and adder array w ith flip-flops fabricated in a 40 nm CMOS process. Measurement results show that IRC reduces the clock power by 36% at 980 kHz and the clock leakage power by 81% compared with conven tional non-resonant clocking when IRC is applied to the adder array with latches. The same power reduction is achieved when IRC is applied to the adder array with flip-flops. IRC can redu ce the clock power at any clock frequency, which enables flexible selection of the clock frequency.