A 100–800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving 40 dBc for ALL Harmonics Saqib Subhan, Student Member , IEEE, Eric A. M. Klumperink , Senior Member , IEEE,A m i r G h a f f a r i

Abstract

Radio transceivers capable of dynamic spectrum ac- cess require frequency-agile transmitters with a clean output spec- trum. High- filters are dif ficult to implement on chip and have limited tuning range. Transmitters with high linearity and broad- band harmonic rejection can be more flexible and require less fil- tering. However, traditional harmonic rejection mixers suppress only a few harmonics. This pape r presents an 8-path polyphase transmitter, which exploits mixer-LO duty-cycle control and a tun- able first-order RC low-pass filter to suppress ALL harmonics to below 40 dBc. The optimum duty-cycle theoretically is 43.65% and a resolution of better than 0.1% is required to keep the spread in harmonic rejection within 1 dB. We propose a simple monotonic duty-cycle control circuit and show by design equations and mea- surements that it achieves the re quired resolution over three oc- taves of frequency range. Also, analysis indicates that LO duty - cycle reduction compared with 50% improves power upconverter efficiency. A transmitter realized in 0.16- m CMOS works from 100 to 800 MHz at a maximum single-tone output power of 10 .8 d B mw i t ha ne fficiency of 8.7%, outperforming previous designs. The OIP3 is 21 dBm, while the LO leakage and image rejection is better than 45 dBc.