A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < –61dB at 2.8 GS/s With DEMDRZ Technique Wei-Te Lin, Student Member , IEEE, Hung-Yi Huang , Student Member , IEEE,a n d T a i - H a u rK u o, Member , IEEE

Abstract

For current-steering digital-to-analog converters (DACs), a technique utilizing d ynamic-element-matching and digital return-to-zero, called D EMDRZ, is proposed to simultane- ously suppress the mismatch- and transient-induced nonlinearity. In doing so, the usage of small-sized current sources and switches is possible, and the spurious-free dynamic range (SFDR) and intermodulation distortion (IMD) for high signal frequencies can be improved. With the DEMDRZ technique, a 12-bit compact, low-power, high-speed, high-re solution DAC is implemented in TSMC 40 nm CMOS process. The DAC architecture, circuit, and layout designs are presented. The implemented DAC achieves > 70 dB SFDR for signals over the 800 MHz Nyquist bandwidth at 1.6 GS/s and < –61 dB IMD for signals over the 1.4 GHz Nyquist bandwidth at 2.8 GS/s. Further, it dissipates 40 mW with a single 1.2 V supply. The active area of the DAC is 0.016 mm 2,w h i c h is less than 6% of other state-of-the-art 12-bit current steering DACs. Furthermore, the implemented DAC performs best with three common figure-of-merits (FoMs).