A 15-MHz Bandwidth 1-0 MASH ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR

Abstract

A1 - 0M A S H ΣΔ analog-to-digital converter (ADC) demonstrates a digital linearization technique for the first time treating integrator distortion with memory and capacitor mis- match errors. A two-tap sequent ial polynomial derived from an output-referred error analysis ac curately models the non-ideality of a first-order modulator. The model parameters are extracted by correlating various moments of the ADC digital output with a one-bit pseudorandom noise ( PN) superimposed on the input, largely reducing the circuit overhead associated with the nonlinear calibration. The prototype ADC employing ampli fiers with a gain of roughly 30 dB measures an 85-dBc spurious-free dynamic range (SFDR) and a 67-dB signal-to-noise and distortion ratio (SNDR) for a 1.1- ( 1-dBFS), 4.99-MHz sinusoidal input at 240 MHz sampling clock (8× OSR) with a 7.5-msec calibration time. For a 1.1- two-tone input at 14.9 MHz and 15.1 MHz, the third-order intermodulation product (IM3) after calibration is 87.1 dBc, which is over 30 dB better than that without calibra- tion. The core ADC consumes 37 mW from a 1.25-V supply and occupies 0.28 mm 2in a 65-nm CMOS low-leakage digital process in which the transistor threshold voltages are around 0.5 V.