← 返回 JSSC 论文列表JSSC 2014第3期RF & Wireless32nm SOI CMOS
A CMOS 210-GHz Fundamental Transceiver With OOK Modulation Zheng Wang, Student Member , IEEE , Pei-Y uan Chiang , Student Member , IEEE , Peyman Nazari, Student Member , IEEE
32nm SOI CMOS工艺下实现的210GHz OOK调制收发器
VCO输出功率13.5dBm, PA增益15dB, LNA增益18dB, EIRP 15.2dBm
太赫兹OOK调制片上天线功率放大器低噪声放大器
▸创新点1：双堆叠交叉耦合VCO，采用双堆叠结构提升输出功率，在210 GHz频率下实现13.5 dBm的高输出功率，显著提升了毫米波频段的振荡器性能。
▸创新点2：基于巴伦的差分功率分配网络，通过新型巴伦结构实现高效的功率分配，优化了信号传输的对称性和效率，支持多PA阵列的协同工作。
▸创新点3：非相干直接检测接收架构，简化了接收机设计，通过LNA和功率检测器的组合实现低噪声（NF=11 dB）和高增益（18 dB），适用于高频非相干通信。
▸创新点4：2x2空间组合阵列与片上天线集成，首次在200 GHz频段实现CMOS收发器，结合PA阵列和天线设计，达到15.2 dBm的EIRP，突破了高频CMOS电路的性能限制。
Abstract
This paper presents a 210-GHz transceiver with OOK modulation in a 32-nm SOI CMOS process 250/320 GHz . The transmitter (TX) employs a2 2 spatial combining array consisting of a double-stacked cross-coupled voltage controlled oscillat or (VCO) at 210 GHz with an on-off-keying (OOK) modulator, a power ampli fier (PA) driver, a novel balun-based differential power distribution network, four PAs, and an on-chip 2 2 dipole antenna arr ay. The noncoherent receiver (RX) utilizes a direct detection architecture consisting of an on-chip antenna, a low-noise ampli fier (LNA), and a power detector. The VCO generates measur ed 13.5-dBm output power, and the PA shows a measured 15-dB gain and 4.6-dBm .T h e LNA exhibits a measured in-band gain of 18 dB and minimum in-band noise figure (NF) of 11 dB. The TX achieves an EIRP of 5.13 dBm at 10 dB back-off from saturated power. It achieves an estimated EIRP of 15.2 dBm when the PAs are fully driven. This is the first demonstration of a fundamental frequency CMOS transceiver at the 200-GHz frequency range.