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JSSC 2014第3期Clocking & PLLs55nm

A Power-Scalable DCO for Multi-Standard GSM/WCDMA

一种功耗可调的DCO设计,通过互补开关对结构实现75%功耗降低且保持相位噪声性能不变
55nm CMOS, 4GHz, 129.3dBc/Hz@2MHz(P-N), 134.7dBc/Hz@2MHz(N-only), FoM 185dBc/Hz
数字控制振荡器多标准频率合成器相位噪声功耗优化GSM/WCDMA
可重构功耗的DCO设计
互补开关对拓扑结构实现功耗优化
保持LC谐振腔不受干扰的相位噪声稳定性
Abstract
A Digitally Controlled Oscillator (DCO) whose power consumption can be reconfigured while maintaining an almost con- stant phase-noise figure-of-merit (FoM). This is achieved by using either a single-switch-pair or a complementary (i.e., double-switch- pair) oscillator topology, without disturbing the optimized LC tank of the DCO. The optimal p ower consumption in the complemen- tary (P-N) configuration is reduced by 75% compared to the single- switch-pair (N-only) configuration, while the FoM is kept constant. Measurements on a 55 n m CMOS 4 GHz DCO prototype show a minimum phase noise of 129.3 dBc/Hz at 2 MHz offset from the carrier in the P-N con figuration, and of 134.7 dBc/Hz in the N-only con figuration, with a phase noise difference very close to the 6 dB expected from theory. The current consumption is 6 mA and 24 mA, respectively, resulting in approximately the same FoM of 185 dBc/Hz.