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A Self-Duty-Cycled and Synchronized UWB Pulse-Radio Receiver SoC With Automatic Threshold-Recovery
一款自同步、自循环的超宽带脉冲无线电接收器SoC，用于低数据率通信，具有高能效。
65 nm LP CMOS, 375 pJ/bit, 79.5 dBm sensitivity
超宽带脉冲无线电自循环低功耗同步
▸创新点1：自动模拟阈值恢复解调器（电路创新）。该解调器通过自动调整模拟阈值，显著提高了接收信号的准确性和稳定性，降低了误码率，适用于低数据率通信。
▸创新点2：全数字时钟和数据恢复同步器（系统创新）。该同步器采用全数字设计，实现了高效的时钟和数据恢复，确保了接收器与发射脉冲流的精确同步，提升了系统整体性能。
▸创新点3：自循环架构（系统创新）。该架构通过自循环机制，实现了接收器的自动开关，显著降低了功耗，结合偏置电路的自循环设计，达到了375 pJ/bit的极低功耗。
▸创新点4：高能效UWB脉冲无线电接收器（系统创新）。该接收器在3.6–5 GHz频段工作，通过高能效设计，实现了79.5 dBm的灵敏度和1 Mbps的传输速率，适用于低功耗应用场景。
Abstract
A fully self-duty-cycled and synchronized UWB pulse-radio receiver SoC targeted at low-data-rate communi- cation is presented. The receiver uses pulse-radio UWB in the 3.6–5 GHz band to achieve a high energy ef ficiency. The proposed architecture employs a a demodulator with an automatic analog threshold-recovery and an all-d igital clock-and-data-recovery synchronizer. The SoC synchronizes with the incoming pulse stream from the transmitter and duty-cycles itself. The SoC prototype achieves a 79.5 dBm, 1 Mbps-norma lized sensitivity for a mere 375 pJ/bit of power consumption in 65 nm LP CMOS, with aggressive duty-cycling ( 30 ns ON times) combined with bias circuit duty-cycling. The SoC is fully integrated to achieve RF-in to bit-out operation and can interface with off-chip, low speed digital components.