A Switchable Digital–Analog Low-Dropout Regulator for Analog Dynamic V oltage Scaling Technique Wei-Chung Chen, Student Member , IEEE, Su-Yi Ping, Tzu-Chi Huang, Y u-Huei Lee , Student Member , IEEE

Abstract

Dual dynamic voltage scal ing (DVS) techniques em- ployed in single-inductor dual-output (SIDO) converters are used to improve the ef ficiency of the system-on-a-chip (SoC). One DVS technique for digital circuits is controlled by the SoC processor. This paper presents the analog DVS (ADVS) technique for analog circuits to scale voltage across the power MOSFET of the switch- able digital–analog (D/A) low-dropout (LDO) regulator which is the post-regulator cascaded in series with the SIDO converter. The ADVS determines the tradeoff between voltage suppression and ef- ficiency. Furthermore, because of the digital operation of the D/A LDO regulator, the quiescent current is further reduced at light loads while the load current requirement is minimized. In addi- tion, the limitation of the capacitor-free LDO is signi ficantly re- duced by a few microamperes. The test chip was fabricated using a 40-nm CMOS process. Experimental results demonstrated switch- able D/A LDO regulator operation with peak efficiency at 96.7% in analog operation and a 5-mV output voltage ripple at 120-mA load resulting from the advantage of ripple suppression. The power ef- ficiency could be sustained at a value over 92.57% even when the load current decreased to 1 A.