Co-Design of a CMOS Recti fier and Small Loop Antenna for Highly Sensitive RF Energy Harvesters Mark Stoopman, Student Member , IEEE , Shady Keyrouz , Student Member , IEEE

Abstract

In this paper, a design method for the co-design and integration of a CMOS recti fier and small loop antenna is described. In order to improve the s ensitivity, the antenna-rectifier interface is analyzed as it plays a crucial role in the co-design optimization. Subsequently, a 5-s tage cross-connected differential rectifier with a 7-bit binary-weighted capacitor bank is designed and fabricated in standard 90 nm CMOS technology. The recti fier is brought at resonance with a high-Q loop antenna by means of a control loop that compensates for any variation at the an- tenna-rectifier interface and passively boosts the antenna voltage to enhance the sensitivity. A complementary MOS diode is pro- posed to improve the harvester’s ability to store and hold energy over a long period of time during which there is insuf ficient power for recti fication. The chip is ESD protected and integrated on a compact loop antenna. Measurem ents in an anechoic chamber at 868 MHz demonstrate a –27 dBm sensitivity for 1 V output across a capacitive load and 27 meter range for a 1.78 W RF source in an office corridor. The end-to-end power conversion ef ficiency equals 40% at –17 dBm.