Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator WooSeok Kim, Student Member , IEEE, Jaejin Park

Abstract

This paper presents a dual-loop ADPLL suitable for video pixel clock generation. Th e dual-loop architecture where a fast subloop works as a DCO inside a main loop is chosen since it can efficiently suppress the ring oscillator phase noise. In order to satisfy a wide tuning range and fine resolution requirements in the pixel clock PLL, the TDC and DCO with two-step and bottom-up control are employed. An s-domain model is utilized to tune the loop parameters so that the dual-loop PLL has the optimum jitter performance. The measurement results match well with the pro- posed s-domain model and clearly show the effectiveness of the dual loop in suppressing the phase noise of the DCO. We propose a new cell-based layout techniq ue to avoid performance degrada- tion during automatic placement and routing, which is compatible with the conventional digital design environment. A chip that oc- cupies 0.032 mm has been fabricated in the 28-nm CMOS tech- nology. The synthesized DCO shows 1.7-LSB DNL which is close to a full-custom layout. The rms integrated jitter is only 15 ps at 250 MHz, even though PLL operates at the extremely low input frequency of 100 kHz. Power consumption is 3.1 mW at 250 MHz with a 1.0-V supply.