Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM

Abstract

The majority of the power consumption of a high- throughput LDPC decoder is spent on memory. Unlike in a gen- eral-purpose processor, the memory access in an LDPC decoder is deterministic and the access win dow is short. We take advantage of the unique memory access characteristic to design a non-refresh eDRAM that holds data for the necessary access window, and fur- ther improve its access time by trading off the excess retention time. The resulting 3T eDRAM cell is designed to balance wordline cou- pling to reliably retain data for a fast access. We integrate 32 5x210 non-refresh eDRAM arrays in a row-parallel LDPC decoder suit- able for the IEEE 802.11ad standard. Memory refresh is eliminated and random access is replaced with a simple sequential addressing. With row merging and dual-frame processing, the 1.6 mm 2 65 nm LDPC decoder chip achieves a peak throughput of 9 Gb/s at 89.5 pJ/b, of which only 21% is spent on eDRAMs. With voltage and frequency scaling, the power consumption of the LDPC decoder is reduced to 37.7 mW for a 1.5 Gb/s throughput at 35.6 pJ/b.