A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS Brian P . Ginsburg, Member , IEEE, Srinath M. Ramaswamy , Member , IEEE, Vijay R entala, Member , IEEE

Abstract

T h i sp a p e rp r e s e n t sa1 6 0G H zc e n t e rf r e q u e n c y pulsed 65 nm CMOS transceiver for short range radar appli- cations. Four phased array transceivers were implemented in a single chip with antennas implemented in a BGA package. The implemented transmitter is c apable of producing pulses of 100 ps widths ( 20 GHz RF bandwidth) at a 160 GHz carrier fre- quency. The measured effective isotropic radiated power (EIRP) is 18.8 dBm for continuous wave outputs. The analog beam forming receiver achieves an overall gain of 42.5 dB, 14 dBm , 7 GHz bandwidth, and a noise figure of 22.5 dB. The sliding window time-dilation baseband relaxes the output data rate and subsequent digital processing requirements. Fine grained duty cycling reduces power dissipation. The entire chip consumes 2.2 W from 1.2/1.4 V supplies in a 65 nm digital CMOS process.