A 3 GHz Dual Core Processor ARM Cortex TM-A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide V oltage Range and Energy Efficiency Optimization David Jacquet, Frédéric Hasbani, Philippe Flatresse

Abstract

This paper presents the implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM-A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology. The im- plementation is based on a fully synthesizable standard design flow. The design exploits the important flexibility pro vided by the FD-SOI technology, notab ly a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.52 V to 1.37 V , and Forward Body Bias (FBB) techniques up to 1.3 V. Detailed expla- nations of the body-biasing techniques speci fic to this technology are largely presented, in the context of a multi- co-integration, which enable this energy ef ficient silicon i mplementation. The system integrates all the advanced IPs for energy ef ficiency as well as the body bias generator and a fast (µs range) dynamic body bias management capability. The measured dual core CPU maximum operation frequency is 3 GHz (for 1.37 V) and it can be operated down to 300 MHz (for 0.52 V) in full continuous DVFS. The obtained relative performance , with respect to an equivalent planar 28 nm bulk CMOS chip, shows an improvement of +237% at 0.6 V , or +544% at 0.61 V with 1.3 V FBB.