← 返回 JSSC 论文列表JSSC 2014第4期Power Management65nmTDC
A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register KwangSeok Kim, Student Member , IEEE ,W o n S i k Y u, Student Member , IEEE ,a n d
提出一种65纳米工艺下的9位112皮秒分辨率流水线时间数字转换器
112 ps分辨率, 250 MS/s, 15.4 mW功耗
时间数字转换器流水线架构高分辨率65纳米CMOS无校准
▸创新点1：新型时间寄存器设计（电路创新） - 提出了一种能够存储、加减时间信息并与时钟信号同步的新型时间寄存器，显著提高了时间信息处理的灵活性和精度，支持流水线操作。
▸创新点2：2.5位/级流水线架构（系统创新） - 采用2.5位/级的流水线架构，结合脉冲序列时间放大器，实现了9位同步流水线TDC，提升了转换速度和分辨率（112 ps分辨率）。
▸创新点3：无校准高分辨率（方法创新） - 在不依赖任何校准技术的情况下，实现了1.12 ps的高时间分辨率和250 MS/s的采样率，显著降低了系统复杂度并提高了可靠性。
▸创新点4：优化的功耗性能（电路创新） - 在65 nm CMOS工艺下，仅消耗15.4 mW功耗，实现了最佳能效比（FoM），展示了高效的功耗管理设计。
Abstract
In this paper, a 2.5 b/stage pipelined time-to-digital converter (TDC) is presented. For pipelined operation, a novel time-register is proposed which is capable of storing, adding and subtracting time information with a clock signal. Together with a pulse-train time-ampli fier, a 9-bit synchronous pipelined TDC is implemented, which consists of three 2.5 b/stage TDCs and a 3 b delay-line TDC. A prototype chip fabricated in 65 nm CMOS process achieves 1.12 ps of time resolution at 250 MS/s while consuming 15.4 mW. Compared to other high-resolution state-of-the-art TDCs, the propo sed pipelined TDC achieves the best figure-of-merit (FoM) without any calibration.