A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface Masum Hossain, Farrukh Aquil, Pak

Abstract

A 800 Mb/s to 3.2 Gb/s memory interface is designed that achieves 30% improved energy ef ficiency by eliminating idle mode power completely. The link is similar to a standard DDR architecture with the addition of a fast-lock DLL on the memory side that wakes up from 0 mW and locks within 3 clock cycles con- suming 24 mW with residual timing error less than 33 mUI. Fol- lowing initial lock, the DLL opera tes in a closed loop to compen- s a t ef o rV , Td r i f tc o n s u m i n g6m W@1 . 6G H zi n c l u d i n gar e p l i c a buffer. By incorporating an inject ion locked oscillator inside the loop, the DLL provides PLL like high frequency input jitter fil- tering, and corrects ±10% DCD without an additional duty cycle correction loop.