← 返回 JSSC 论文列表JSSC 2014第4期Data Converters0.13μmPipeline ADCDAC
A Time-Based Pipelined ADC Using Both V oltage and Time
提出一种结合电压和时间域信息的基于时间的流水线ADC，提高分辨率和能效。
69.3 dB SNDR, 6.38 mW, 70 MHz
时间域ADC流水线ADC电压时间转换能效优化混合域处理
▸创新点1：系统创新 - 结合电压和时间域信息，提出了一种新型的混合域流水线ADC架构，通过电压域处理MSB和时间域处理LSB，显著提高了分辨率和能效，实现了69.3 dB的峰值SNDR和38.2 fJ/conversion-step的FOM。
▸创新点2：电路创新 - 采用低增益放大器（仅24 dB直流增益）实现高精度的电压-时间（V-T）转换，简化了电路设计并降低了功耗，同时保持了高转换精度。
▸创新点3：电路创新 - 后端采用混合时间域流水线级，结合简单的电荷泵和电容DAC设计，进一步提升了能效，同时支持70 MHz的高采样频率。
▸创新点4：方法创新 - 通过优化电压域和时间域的信号处理分工，实现了高效的资源分配，降低了整体系统的复杂度，同时保持了高性能指标。
Abstract
In this paper, a Nyquist ADC with a time-based pipelined TDC is proposed. In the proposed ADC, the first pipeline stage incorpor ates both residue ampli fication and a V-T conversion with high accuracy, ef ficiently realized by a low gain amplifier with only 24 dB dc gain. Furthermore, adding to power efficiency, a hybrid time-domain pipeline stage based on simple charge pump and capacitor DAC in its backend stages is also proposed. Using the right combination of voltage and time do- main information, the proposed ADC architecture bene fits from improved resolution and power ef ficiency, with MSBs resolved in voltage domain and LSBs in time domain. The measured results of the prototype ADC implemented in a 0.13 mC M O Sd e m o n s t r a t e peak SNDR of 69.3 dB at 6.38 mW power and 70 MHz sampling frequency. The FOM based on peak SNDR is 38.2 fJ/conver- sion-step.