Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process V ertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme Meng-Fan Chang, Chia-Chen Kuo, Shyh-Shyuan Sheu, Chorng-Jung Lin, Y a-Chin King, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Jui-Jen Wu, and Y ue-Der Chih

Abstract

The design of resistive RAM (ReRAM) faces two major challenge s: 1) cell area versus write current requirements and 2) cell read current ( ) versus read disturbance. This paper proposes ReRAM macros using logic-process-based vertical parasitic-BJT (VPBJT) switches and a corresponding cell array (VPBJT-CA), resulting in a 4.5× macro density compared to conventional NMOS-switch ReRAM for given write current re- quirements. To overcome temperature-dependent fluctuations in the base-emitter voltage difference ( )o fV P B J T ,w ep r o p o s e a temperature-aware bitline (BL) voltage bias (TABB) scheme t o provide current-mode sensing with 4.7× larger and 1.6× faster read speeds. Test results of fabricated 0.18 µm 1 Mb and 65 nm 2 Mb VPBJT ReRAM macros con firm the efficacy of the temperature-aware , resulting in sub-5-ns random read access times.