A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS

Abstract

A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop ( ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. The fractional-N ADPLL employs a high-resolution 60 GHz digitally- controlled oscillator (DCO) and is capable of multi-rate two-point FM. It achieves a measured rms jitter of 590.2 fs, while the loop set- tles within 3 µs. The measured reference spur is only –74 dBc, the fractional spurs are below –62 dBc, with no other signi ficant spurs. A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multi ple DCO tuning banks with a mea- sured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHz rms for a 62 GHz carrier with 1.22 GHz bandwidth. The synthesizer is transformer- coupled to a 3-stage neutralized power ampli fier (PA) that delivers +5 dBm to a 50 Ω load. Imple- mented in 65 nm CMOS, the transmitter prototype (including PA) consumes 89 mW from a 1.2 V supply.