← 返回 JSSC 论文列表JSSC 2014第5期Data Converters40nmSAR ADC
A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range Badr Malki, Student Member , IEEE , Takaya Yamamoto, Bob V erbruggen , Member , IEEE
一种采用自适应动态范围的70dB DR 10位0至80MS/s电流积分SAR ADC
40nm CMOS, 1.1V, 0-80MS/s, 70dB DR, 56.85dB SNDR@40MS/s
SAR ADC电流积分可变增益跨导器非线性MOS电容自适应动态范围
▸创新点1：采用可变增益跨导器电流积分于采样电容，替代传统功耗高的电压缓冲器驱动，显著降低功耗（1.1V供电下总电流<5.45mA），属于电路级创新
▸创新点2：利用非线性MOS电容的被动放大特性作为采样电容，在不牺牲线性度的前提下降低比较器噪声要求（实现70dB动态范围），属于器件级方法创新
▸创新点3：自适应动态范围技术通过动态调节跨导器增益（1.1–17.6 mS可调），使ADC在0-80MS/s速率范围内保持56.85dB峰值SNDR，属于系统级控制创新
▸创新点4：电荷共享型SAR ADC架构结合电流积分机制，在40nm CMOS工艺下实现10bit精度与80MS/s采样率的协同优化，属于混合架构创新
Abstract
A charge-domain SAR ADC is presented which integrates the current of a varia ble-gain transconductor on its sampling capacitor, rather than being driven by a power hungry voltage buffer. The sampling circuit uses nonlinear MOS capac- itors as sampling capac itor for passive ampli fication to relax the comparator noise requirements without compromising linearity. The prototype in 40 nm low power CMOS process consists of a 1.1–17.6 mS transconductor, combined with a 10 b 0–80 MS/s charge-sharing SAR ADC. It achieves 70 dB DR while consuming less than 5.45 mA from a 1.1 V supply and achieves a peak SNDR of 56.85 dB at 40 MS/s.