← 返回 JSSC 论文列表
📄 下载 JSSC 原文 PDF
JSSC 2014第5期Data Converters90nmVCOTDC

A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators—Analysis, Design, and

提出一种基于开关环形振荡器的高分辨率时间数字转换器,无需校准即可实现噪声整形。
90nm CMOS, 1V, 500MS/s, 315fs噪声, 1.5mW功耗
时间数字转换器噪声整形开关环形振荡器高分辨率过采样
创新点1:使用开关环形振荡器(SRO)实现噪声整形,通过切换环形振荡器的频率,在开环方式下对量化误差进行噪声整形,无需校准即可实现高分辨率。
创新点2:解耦采样时钟和输入载波频率,使得SRO-TDC能够在高过采样比(OSR)下工作,显著提升了系统的灵活性和性能。
创新点3:在90 nm CMOS工艺下实现,支持宽范围的输入载波频率(0.6–750 MHz)和采样率(50–750 MS/s),在500 MS/s和80 MHz载波频率下,集成噪声仅为315 fs,功耗仅为1.5 mW。
创新点4:提出了一种新的技术来表征TDC的线性度、范围和噪声性能,为噪声整形TDC的设计和优化提供了有效的工具。
Abstract
A high-resolution time-to-digital converter (TDC) using switched-ring oscillator s (SROs) is presented. Leveraging oversampling and noise shaping, the proposed SRO-TDC achieves high resolution without the need for calibration. Ring oscillators are switched between two frequencies to achieve noise shaping of the quantization error in an open-loop manner. By decoupling the sampling clock and input carrier frequencies, SRO-TDC is ca- pable of operating at high oversam pling ratios (OSRs). This paper also discusses different noise s ources and quantization/device noise tradeoffs in noise-shaping TDCs and presents techniques to characterize TDC linearity, range, and noise performance. Fab- ricated in 90 nm CMOS technology, the proposed TDC operates over a wide range of input carrier frequencies (0.6–750 MHz) and sampling rates (50–750 MS/s). At 500 MS/s and 80 MHz carrier frequency, it achieves an integrated noise of 315 fs in a 1 MHz bandwidth while consuming 1.5 mW from a 1 V supply. The SRO-TDC occupies an active die area of only 0.02 mm .