An Energy Ef ficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS Dongsuk Jeon, Student Member , IEEE, Michael B. Henry, Y ejoong Kim, Inhee Lee , Student Member , IEEE

Abstract

This paper presents an energy-ef ficient feature ex- traction accelerator design aim ed at visual navigation. The hard- ware-oriented algorithmic modi fications such as a circular-shaped sampling region and uni fied description are proposed to minimize area and energy consumption while maintaining feature extraction quality. A matched-throughput accelerator employs fully-unrolled filters and single-stream descriptor enabled by algorithm-archi- tecture co-optimization, which requires lower clock frequency for the given throughput requirement and reduces hardware cost of description processing elements. Due to the large number of FIFO blocks, a robust low-power FIFO architecture for the ultra-low voltage (ULV) regime is also proposed. This approach leverages shift-latch delay elements and b alanced-leakage readout tech- nique to achieve 62% energy savings and 37% delay reduction. We apply these techniques to a fea ture extraction accelerator that can process 30 fps VGA video in real time and is fabricated in 28 nm LP CMOS technology. The design consumes 2.7 mW w i t hac l o c kf r e q u e n c yo f2 7M H za t 470 mV , providing 3.5× better energy ef ficiency than previous state-of-the-art while extracting features from entire image.