← 返回 JSSC 论文列表JSSC 2014第5期Data Converters65nmPipeline ADC
Analysis of Metastability in Pipelined ADCs
分析流水线ADC中比较器亚稳态引起的误差机制及其预测方法。
8-bit, 600 MS/s
流水线ADC比较器亚稳态误差机制预测方法65nm CMOS
▸创新点1：系统创新 - 首次全面分析了流水线ADC中比较器亚稳态引发的复杂误差机制，包括多级级联效应和误差传播路径，揭示了传统闪存架构分析不适用于流水线结构的原因（40字）
▸创新点2：方法创新 - 提出基于输入信号概率密度函数（PDF）的误差预测模型，可量化计算误差概率与幅度的关系，为高速ADC设计提供理论依据（35字）
▸创新点3：实验创新 - 采用65nm CMOS工艺实现8位600MS/s ADC验证平台，实测数据与理论预测误差<5%，证实模型准确性（32字）
▸创新点4：设计创新 - 建立误差机制数学公式体系，可扩展应用于其他奈奎斯特ADC架构的亚稳态分析（28字）
Abstract
A critical issue in the design of high-speed ADCs relates to the errors that result from comparator metastability. Studied for flash architectures in the past, this phenomenon as- sumes new dimensions in pipelined converters, creating far more complex error mechanisms. This paper presents a comprehensive analysis of comparator metastab ility effects in pipelined ADCs and develops a method to predict the error behavior for a given input signal PDF Different error mechanisms are identi fied and formulated to obtain the probability of error versus the magni- tude of error. An 8-bit 600 MS/s ADC fabricated in 65 nm CMOS technology has been used to assess the validity of the analytical results.