← 返回 JSSC 论文列表JSSC 2014第6期Data Converters45nm CMOS SOIDAC
A 10 bit, 300 MS/s Nyquist Current-Steering Power DAC With 6 V Output Swing Mohammad S. Mehrjoo , Student Member , IEEE, and James F. Buckwalter , Senior Member , IEEE
一款10位300MS/s电流导向DAC,采用堆叠FET缓冲实现6V输出摆幅。
10位, 300MS/s, 6V输出摆幅, 476mW功耗, SFDR 73dB, IM3 -69dBc
电流导向DAC堆叠FET缓冲高输出摆幅Volterra分析功率效率
▸采用堆叠FET缓冲隔离电流源与输出负载
▸提出Volterra分析量化堆叠FET电路的线性度
▸实现高分辨率高速DAC的最大输出摆幅和最高功率效率
Abstract
A 10 bit current-steering, digital-to-analog converter (DAC) is presented that delivers 6 V into a 100 Ω differen- tial load. To realize high-voltage swings using fineline CMOS, a stacked-FET buffer is used to isolate the current source from the output load. The stacked-FET buffer degrades the linearity of the DAC. This work presents a Volterra analysis to capture the frequency-dependent behavior of the stacked-FET circuit that can be cascaded to quantify the linearity of an -device stack. T h ep o w e rD A Ci si m p l e m e n t e di n4 5n mC M O SS O Ia n dt h e measured differential nonlinearity (DNL) and integral nonlin- earity (INL) is better than 0.4 an d 0.6 LSB, respectively. The DAC consumes 476 mW and achieve s a peak SFDR of 73 dB and a minimum IM3 of 69 dBc. This DAC demonstrates the largest output swing and highest power ef ficiency for a high-resolution ( 8 bit), high-speed ( 100 MS/s) DAC.