A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue

Abstract

A 12 bit 200 MS/s anal og-to-digital converter (ADC) applies techniques of zero-crossing-based circuits as a replacement for high-gain high-speed op-amps. High accuracy in the residue amplifier is achieved by usi ng a coarse phase in ZCBC followed by a level-shifting capacitor for fine phase. Sub-ADC flash com- parators are strobed immediately after the coarse phase to achieve ah i g hs a m p l i n gr a t e .The systematic offset voltage between the coarse and fine phase manifests itself as systematic offset in the sub-ADC comparators. This offset is caused by the coarse phase undershoot and t he fine phase overshoot. In this work, the offset is cancelled with background calibration by residue range correc- tion circuits in the following stage’s sub-ADC. In addition, the sub- ADC’s random comparator offset is calibrated with a discrete-time charge-pump based background ca libration technique. The ref- erence buffer, bias circuitry, and digital error correction circuits are all i ntegrated on a single chip. The ADC occupies an area of 0.282 mm in 55 nm CMOS technology and dissipates 30.7 mW. It achieves 64.6 dB SNDR and 82.9 dBc SFDR at 200 MS/s for a FOM of 111 fJ/conversion-step. The SNDR degrades gracefully above the designed sampling frequency to 62.9 dB at 250 MS/s, and remains above 50 dB at 300 MS/s.