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JSSC 2014第6期RF & Wireless65nmNeural Network Accelerator

A 2.4 GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter Topology in 65 nm CMOS

65nm CMOS工艺下集成了Blixer和基带混合滤波器的24 GHz ZigBee接收器
65nm CMOS, 8.5 dB NF, 57 dB增益, 6-dBm IIP3, 1.7 mW功耗, 0.24 mm²芯片面积
ZigBee接收器Blixer电流复用噪声整形CMOS
RF到基带电流复用的Blixer结构
集成低Q网络实现宽带输入匹配与无源预增益
IF噪声整形电流模式Biquad与复极点负载实现滤波
Abstract
A2 . 4G H zZ i g B e er e c e i v e ru n i f y i n gab a l u n - LNA-I/Q-mixer (Blixer) and a baseband (BB) hybrid filter in one cell is fabricated in 65 nm CMOS. Without any external components, wideband input ma tching and passive pre-gain are concurrently achieved via co-optimizing an integrated low-Q network with a balun-LNA. The latter also features active-gain boosting and partial-noise ca nceling to enhance the gain an dn o i s e figure (NF). Above the balun-LNA are I/Q double-balanced mixers driven by a 4-phase 25% LO for dow nconversion and gain-phase balancing. The generated BB currents are immediate ly filtered by an IF-noise-shaping current-mode Biquad and a complex-pole load, offering first-order image rejection and third-order channel selection directly atop the Blixer. Together wit ho t h e rB Ba n d LO circuitries, the receiver measures 8.5 dB NF, 57 dB gain and 6-dBm IIP3 at 1.7 mW power and 0.24 mm die size. The S -bandwidth ( 10 dB) covers 2.25 to 3.55 GHz b eing ro- bust to packaging variations. Most performance metrics compare favorably with the state-of-the-art.