← 返回 JSSC 论文列表JSSC 2014第7期Data Converters65nmDACOp-Amp
A 0.039 mm Inverter-Based 1.82 mW 68.6 dB-SNDR 10 MHz-BW CT- -ADC in 65 nm CMOS Using Power- and Area-Ef ficient
提出了一种基于逆变器的低功耗连续时间ΔΣ ADC设计，采用65纳米CMOS工艺实现高性能
65nm CMOS, 1.1V, 686dB-SNDR, 10MHz带宽, 182mW功耗
逆变器低功耗ΔΣ ADCCMOS数字辅助
▸创新点1：谐振单运放三阶积分器，采用谐振技术和损耗补偿，显著提高了积分器的线性度和带宽，适用于超深亚微米CMOS工艺。
▸创新点2：数字辅助偏置的逆变器运放，通过数字辅助偏置和共模控制，优化了逆变器运放的性能和功耗，实现了低功耗和高精度。
▸创新点3：伪差分调制器拓扑结构，采用准1.5位量化技术，提高了调制器的抗噪声能力和动态范围，适用于高精度ADC设计。
▸创新点4：抖动噪声降低DAC，采用NRZ脉冲形状，有效降低了抖动噪声，提高了DAC的稳定性和精度。
Abstract
We present design techniques for the realization of compact, low-power CT- -ADCs in ultra-deep-submicron CMOS: A resonant single-opamp third-order integrator with loss compensation, an inverter-based opamp with digitally assisted bi- asing and common mode control, a ps eudo-differential modulator topology with quasi-1.5-bit quantization, a jitter-noise-reduction DAC with NRZ pulse shape, a mismatch-tolerant IIR quantizer, linearized single-ended FIR-DAC s with passive DT compensation, and a rail-to-rail dynamic latched comparator. A highly compact 41.4 fJ/conv.-step, 77 dB-SFDR, 1.1 V ADC has been implemented t op r o v et h e s ec o n c e p t s .T h ee n t i r ea c t i v ea n a l o gc i r c u i t r yi nt h i s minimalistic third-order modulator consists of only ten CMOS inverters.