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JSSC 2014第7期RF & Wireless65nm

A Filtering ΔΣ ADC for LTE and Beyond

提出一种用于LTE通信的滤波ADC,结合二阶ΔΣ调制器和三阶切比雪夫滤波器,优化噪声抑制性能。
65nm CMOS, 576/288 MHz时钟, 18.5/9.0 MHz带宽, 56.4/58.1 dB SNDR, 7.9/5.4 mW功耗
滤波ADCDelta–Sigma调制器LTE信道选择滤波器噪声抑制
将二阶Delta–Sigma调制器集成到三阶切比雪夫信道选择滤波器中
开发了考虑DSM-DAC延迟的设计方法
实现了对热噪声和量化噪声的额外三阶抑制
Abstract
This paper presents a filtering ADC for the LTE communication standard, where a second-order Delta–Sigma modulator (DSM) is incorporated into the third-order Cheby- chev channel-select filter (CSF) of the radio receiver. The CSF introduces an additional third- order suppression of both thermal and quantization DSM noise, while the CSF transfer function is maintained. A design method for the filtering ADC accounting for unavoidable DSM-DAC delays is developed and experimen- tally demonstrated. The 65 nm CMOS prototype is clocked at 576/288 MHz with an 18.5/9.0 MHz LTE bandwidth, has an in-band gain of 26 dB, an SNDR of 56.4/58.1 dB, an input-referred noise of 5 nV/ , and an out-of-band (half-dup lex) IIP3 of 20/12 dBV rms, with a power consumption of 7.9/5.4 mW and an overall state-of-the art performance.