← 返回 JSSC 论文列表JSSC 2014第7期Digital Circuits32nm
A Fine-Grain V ariation-Aware Dynamic -Hopping A VFS Architecture on a 32 nm GALS MPSoC Ivan Miro-Panades, Edith Beigné, Y vain Thonnart , Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Anca Molnos, Far hat Thabet, Benoit Tain, Karim Ben Chehida, Sylvain Engels, Robin Wilson, and
提出一种32纳米工艺下的细粒度自适应电压频率调节架构，优化多处理器系统芯片的全局能效。
32 nm CMOS, 18.2% energy gains, 10% area overhead
自适应电压频率调节多处理器系统芯片能效优化细粒度控制32纳米工艺
▸创新点1：细粒度自适应电压频率调节，通过局部传感器和数字控制器实时监测工艺、电压和温度变化，动态调整每个处理单元的电压和频率，减少全局时序裕量至60ps，显著提升能效。
▸创新点2：独立电压频率岛设计，每个处理单元作为独立的电压频率岛，支持局部自适应调节，避免了全局动态电压频率调节的时序裕量浪费，实现了18.2%的能效提升。
▸创新点3：动态工艺电压温度变化优化，通过精细的局部适应性调节，有效应对先进工艺节点下的动态变化，减少了传统全局调节所需的25%时序裕量，降低了系统功耗。
▸创新点4：系统架构创新，在32nm全局异步局部同步MPSoC上实现该架构，仅增加10%的面积开销，包括局部频率/电压执行器、传感器和数字控制器，实现了高性能与低功耗的平衡。
Abstract
In order to optimize global energy ef ficiency in the context of dynamic process, voltage and t emperature vari- ations in advanced nodes, a fine-grain adaptive voltage and frequency scaling architecture is proposed for multiprocessor systems-on-chip (MPSoC), where each proc essing element is an independent voltage–frequen cy island. This architecture has been implemented on a 32 nm globally asynchronous locally-syn- chronous MPSoC. It shows up to 18.2% e nergy gains thanks to local adaptability compared with a global dynamic voltage and frequency scaling approach using 25% timing margins between slow and nominal process, by reduc ing margins to 60 ps of the real process. These gains are obtained for a total area overhead of 10% including local frequency/ voltage actuators, sensors, and digital controller.