JSSC 2014第7期RF & Wireless65nmDelta-Sigma ADCDAC

A Wideband 400 MHz-to-4 GHz Direct RF-to-Digital Multimode Receiver Charles Wu, Student Member , IEEE

一款基于65nm CMOS工艺的宽频带直接射频到数字多模接收器，支持400 MHz至4 GHz频率范围。

65nm CMOS, 1.1 V/1.5 V, 40 mW, 68 dB SNDR, 10 dBm IIP3

宽频带直接射频到数字多模接收器CMOS低功耗

▸创新点1：宽频带信号传输功能（系统创新）。通过采用平坦的信号传输函数设计，实现了400 MHz至4 GHz的超宽频带覆盖，支持多频段无线电通信，显著提升了接收器的通用性和适应性。

▸创新点2：多级非归零DAC提高抗抖动能力（电路创新）。采用两比特非归零DAC结构，有效降低了时钟抖动对动态范围的影响，使接收器在宽频带范围内保持高动态范围（SNDR > 60 dB）。

▸创新点3：AB类低噪声跨导放大器保证前端线性度（电路创新）。结合负反馈数字化技术，在近天线端实现高线性度（IIP3达+10 dBm），同时仅消耗40 mW功耗，解决了传统接收器线性度与功耗的矛盾。

▸创新点4：直接射频到数字转换架构（系统创新）。通过Sigma-Delta调制器紧邻天线端的设计，省去传统下变频环节，简化系统结构并降低噪声干扰，实现68 dB峰值SNDR的高性能指标。

Abstract

A wide-tuning-range low-power sigma-delta-based direct-RF-to-digital receiver architecture is implemented in 65 nm CMOS. A ﬂat signal transfer functi on is chosen to support wide-frequency-range radios. A multilevel (two-bit) nonre- turn-to-zero DAC improves jitter immunity to enable a high dynamic range, and, with a class-AB low-noise transconductance ampliﬁer, guarantees a highly linear front end. For a 4 MHz signal, the peak SNDR of the receiver exceeds 68 dB and is better than 60 dB across the 400 MHz to 4 GHz carrier frequency range. By virtue of utilizing a negative feedback digitizer close to the antenna, an IIP3 of 10 dBm is achieved while dissipating only 40 mW from 1.1 V/1.5 V supply voltages.