A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2

Abstract

A software-de fined radio receiver is pres ented, oper- ating from 400 MHz to 6 GHz. The s plit front-end architecture has a low-band RF path (0.4–3 GHz) using 8-phase passive mixers and a high-band RF path (3–6 GHz) using 4-pha se passive mixers. DC-offset, IIP 2, and harmonic recombination for harmonic rejec- tion may be calibrated to achieve true wideband speci fications. A 0.5–50 MHz tunable baseband bandwidth i mplies compliance with LTE and future standards. Despite having a 0.9 V supply, the receiver architecture ensures high out-of-band linearity. The 0.6 mm 2, 28 nm CMOS receiver ach ieves down to 1.8 dB NF, +3 dBm out-of-band IIP3, 70 dB calibrated HR3/5 and +80 dBm calibrated IIP2. It tolerates 0 dBm blockers at 80 MHz offset with a blocker NF of 10 dB f or a power consumption of 20–40 mW.