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A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB Yida Duan, Student Member , IEEE,a n dE l a dA l o n, Senior Member , IEEE
本文介绍了一种12.8 GS/s 32路分层时间交织SAR ADC，采用65 nm CMOS工艺，实现4.6 ENOB和25 GHz有效分辨率带宽。
12.8 GS/s, 4.6 ENOB, 25 GHz ERBW, 0.23 mm², 162 mW
时间交织ADCSAR ADC分层采样级联采样伪差分
▸创新点1：分层采样技术（系统创新）。通过32路分层时间交织采样，显著提升采样率至12.8 GS/s，同时保持高分辨率带宽（ERBW）大于25 GHz。
▸创新点2：级联采样电路（电路创新）。采用级联采样器结构，有效扩展了ADC的有效分辨率带宽，使其在25 GHz时仍能保持26.4 dB的SNDR。
▸创新点3：伪差分SAR ADC（电路创新）。通过伪差分结构设计，降低了功耗和面积，核心电路仅占用0.23 mm²，总功耗为162 mW，实现了0.79 pJ/conversion-step的能效比。
▸创新点4：可扩展架构（系统创新）。设计支持通过增加交织路数扩展至25.6 GS/s或51.2 GS/s，且不影响ERBW，展现了良好的可扩展性。
Abstract
This paper presents a 12.8 GS/s 32-way hierarchically time-interleaved SAR ADC with 4.6 ENOB in 65 nm CMOS. The prototype utilizes hierarchica l sampling and cascode sampler circuits to enable greater than 25 GHz 3 dB effective resolution bandwidth (ERBW). We further employ a pseudo-differential SAR ADC to save power and area. The core circuit occupies only 0.23 mm 2 and consumes a total of 162 mW from dual 1.2 V/1.1 V supplies. The design achieves a SNDR of 29.4 dB at low fre- quencies and 26.4 dB at 25 GHz, resulting in a figure-of-merit of 0.79 pJ/conversion-step. As will be further described in the paper, the circuit architecture used in t his prototype enables expansion to 25.6 GS/s or 51.2 GS/s via additional interleaving without significantly impacting ERBW.