A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function Sigang Ryu, Student Member , IEEE, Hwanseok Y eo, Student Member , IEEE, Y oontaek Lee

Abstract

A 9.2 GHz digital phase-locked loop (PLL) that real- izes a peaking-free jitter transfe r function is presented. In other words, the closed-loop transfer function of the proposed digital PLL does not possess a closed-loop zero and the PLL achieves fast settling without exhibiting overshoots. While most previously re- ported peaking-free PLLs require additional circuit components which may adversely affect clock j itter or increase hardware com- plexity, the presented PLL requires only a new type of digital loop filter. The analysis on the loop dynamics and design of the op- timal loop filter are presented. As for the implementation, a low- power linear time-to-digital converter (TDC) is realized with a set of three binary phase-frequency d etectors whose triggering clocks are dithered using a delta-sigma modulator and phase interpola- tors. A digitally controlled osc illator (DCO) is implemented as a transformer-tuned LC oscillato r whose frequency is set by a ratio between two digitally controlled currents. The digital PLL proto- type, fabricated in a 65 nm CMOS, demonstrates 1.2 ps inte- grated jitter at 9.2 GHz and 1.58 s settling time with 700 kHz bandwidth while dissipating 63.9 mW at a 1.2 V nominal supply.