A Bit-by-Bit Re-Writable E fla s hi naG e n e r i c6 5n m Logic Process for Moderate-Density Nonvolatile Memory Applications Seung-Hwan Song, Ki Chul Chun, and Chris H. Kim , Senior Member , IEEE

Abstract

Embedded nonvolatile memory (eNVM) is considered to be a critical building block in future system-on-chip and mi- croprocessor systems. Various eNVM technologies have been ex- plored for high-density applications including dual-poly embedded flash (eflash), FeRAM, STT-MRAM, and RRAM. On the other end of the spectrum, logic-compatible eNVM such as e-fuse, anti-fuse, and single-poly e flash memories have been considered for mod- erate-density low-cost applications. In particular, single-poly eflash memory has been gaining momentum as it can be implemented in a generic logic process while supporting multiple program-erase cy- cles. One key challenge for single-poly e flash is enabling bit-by-bit re-write operation without a boosted bitline voltage as this could cause disturbance issues in the unselected wordlines. In this work, we present details of a bit-by-bit re-writable e flash memory imple- mented in a generic 65 nm logic process which addresses this key challenge. The proposed 6 T e flash memory cell can improve the overall cell endurance by eliminating redundant program/erase cy- cles while preventing disturbance issues in the unselected word- lines. We also provide details of special high voltage circuits such as a voltage-doubler based charge pump circuit and a multistory high-voltage switch, for generating a reliable high-voltage output without causing damage to the s tandard logic transistors.