An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs Salvatore Levantino,M e m b e r ,I E E E

Abstract

Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in the design of frequency synthesizers for wireless applications. However, the main obstacle to their full acceptance in the wireless-systems arena is their higher content of output spurious tones, whose level is ultimately set by the nonlinearity of the time-to-digital converter (TDC). The known methods to improve the linearity of the TDC either increase its dissipation and phase noise or require slow foreground calibrations. By contrast, the class of digital PLLs based on a one-bit TDC driven by a multibit digital-to-time converter (DTC) substantially reduces power dissipation and eliminates the TDC nonlinearity issues. Although i ts spur performance depends on DTC linearity, the modified architecture enables the application of a background adaptive pre-distortion which does not compromise the PLL phase-noise level and power consumption and is much faster than other calibration techniques. This paper presents a 3.6-GHz digital PLL in 65-nm CMOS, with in-band fractional spurs dropping from 39 to 52 dBc when the pre-distortion is enabled, in-band phase noise of 103 dBc/Hz and power con- sumption of 4.2 mW.