← 返回 JSSC 论文列表JSSC 2014第9期Clocking & PLLs0.18µm
A1 0G b / s ,6Vp-p, Digitally Controlled, Differential Distributed Amplifier MZM Driver
采用0.18µm SiGe-BiCMOS工艺实现的10Gb/s数字控制差分分布式放大器MZM驱动器，输出6Vp-p差分摆幅。
0.18µm SiGe-BiCMOS, 6Vp-p, 10Gb/s, 2.13W
分布式放大器SiGe-BiCMOS马赫-曾德尔调制器数字控制高速驱动
▸创新点1：数字控制差分分布式放大器（电路创新）——采用0.18 µm SiGe-BiCMOS工艺实现，集成宽带n+/n-well背端电阻和衬底屏蔽输出线，在50 Ω负载下产生6 V p-p差分输出摆幅，输出回波损耗优于10 dB（35 GHz以下），显著提升高频信号完整性。
▸创新点2：可调输出边沿速度（方法创新）——通过数字调节实现20–80%上升/下降时间从<15 ps至50 ps的动态范围，适应不同调制器对驱动信号边沿特性的需求，增强系统灵活性。
▸创新点3：全数字输入接口支持多通道扩展（系统创新）——ECL兼容输入灵敏度达65 mV p-p（10 Gb/s单端），集成时钟移相器和数字锁存器，为多级DA级联、多通道输出及摆幅扩展提供标准化数字控制框架。
▸创新点4：高集成度设计（电路创新）——在2.87 mm²芯片面积内集成限幅放大器、背端匹配电阻等模块，采用-5.2 V/5 V双电源供电，总功耗2.13 W，实现驱动与阻抗匹配功能的一体化微型化。
Abstract
A 10 Gb/s, digitally controlled, differential dis- tributed ampli fier (DA) optical modulator driver is implemented in 0.18 µm SiGe-BiCMOS technology. The 2.87 mm 2 prototype integrates clock phase shifters, d igital latches, limiting ampli- fiers, broadband n+/n-well back terminatio n resistors and a substrate-shielded output line on chip. It produces 6 V p-p differ- ential output swing across 50 Ω loads. The output edge speed is trimmable, with 20–80% rise/fall times r anging from < 15 ps to 50 ps at 10 Gb/s. Minimum sensitivity of the ECL-compatible inputs is 65 mV p-p at 10 Gb/s single-ended, with negligible additive jitter. Measured output return loss i s better than 10 dB below 35 GHz, suf ficient to drive an external push-pull Mach-Zehnder optical modulator. Total power c onsumption is 2.13 W operating from –5.2 V and 5 V supplies. The f ully-digital input interface supports scalability in the numbe r of DA stages, output swing and to multiple output channels.