A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network Cong Shi, Student Member , IEEE, Jie Y ang, Y e Han, Zhongxiang Cao, Qi Qin

Abstract

This paper proposes a vision chip hybrid architecture with dynamically recon figurable processing element (PE) array processor and self-organizing map (SOM) neural network. It integrates a high speed CMOS image sensor, three von Neu- mann-type processors, and a non-von Neumann-type bio-inspired SOM neural network. The processors consist of a pixel-parallel PE array processor with parallelism, a row-parallel row-processor (RP) array processor with parallelism and a thread-parallel dual-core microprocessor unit (MPU) with parallelism. They execute low- , mid- and high-level image processing, respectively. The SOM network speeds up high-level processing in pattern recognition tasks by ,w h i c h improves the chip performance remarkably. The SOM network can be dynamically recon figured from the PE array to largely save chip area. A prototype chip with a 256 256 image sensor, a re- configurable 64 64 PE array processor/16 16 SOM network, a6 4 1 RP array processor and a dual-core 32-bit MPU was implemented in a 0.18 m CMOS image sensor process. The chip can perform image capture and various-level image processing at ah i g hs p e e da n di nflexible fashion. Various complicated applica- tions including M-S functional solution, horizon estimation, hand gesture recognition, face recognition are demonstrated at high speed from several hundreds to 1000 fps.