A 2 GS/s Frequency-Folded ADC-Based Broadband

Abstract

A frequency-folded ADC-based broadband sampling receiver that merges sampling within the structure of a broadband downconverter is presented. The receiver channelizes a broad- band input into sub-bands after digitization, while employing digital-domain harmonic and image rejection. The design offers af r equency-domain approach to simultaneously achieving high sample rate and dynamic range per-unit power consumption. Noise and distortion performance of the architecture is described. An analysis of SNR improvement du ring signal reconstruction that results from the use of multiple paths at baseband is pre- sented. A 2 GS/s receiver based on this approach is implemented in a 65 nm CMOS process. The receiver spans a bandwidth from 125 MHz to 1000 MHz, and achieves a mean SNDR of 49 dB across the input bandwidth, while providing 38–43.3 dB of gain and a NF of 8.5–13.4 dB. Equalization-based calibration results in harmonic and image rejection greater than 59 dB and 58 dB, respectively, across the input bandwidth, while even better performance may be achieved for tonal interferers. The receiver consumes 104 mW from a dual 1.2/2.5 V supply.