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JSSC 2014第9期RF & Wireless65nmPLLClock Generation

A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios

一种用于软件定义无线电的紧凑型低功耗分数注入锁定正交频率合成器
65nm CMOS, 10MHz-6.6GHz, 16-26mW, 0.38mm²
频率合成器注入锁定正交相位软件定义无线电低功耗
创新点1:分数注入锁定分频器(ILFD) - 该方法创新通过结合分数-N分频与注入锁定技术,实现了宽频带覆盖(10 MHz至6.6 GHz)和高频率分辨率,同时显著降低功耗(16-26 mW)和面积(0.38 mm²)。
创新点2:自同步门控注入技术 - 该电路创新通过动态控制注入信号的时序,解决了传统ILFD的相位误差问题,提升了锁定范围和稳定性,支持分数-N操作模式。
创新点3:数字校准方案 - 该系统创新通过实时监测PVT变化并调整电路参数,补偿了工艺偏差和环境波动,确保相位噪声性能(-135.3 dBc/Hz @3MHz偏移)。
创新点4:紧凑型正交输出设计 - 该电路创新通过优化PLL与ILFD的耦合结构,在极小面积内实现高质量正交相位输出,满足SDR对多频段信号处理的需求。
Abstract
This paper describes a compact and low-power frequency synthesizer with quadrature phase output for soft- ware-defined radios (SDRs). The proposed synthesizer is con- structed using a core phase-locked loop (PLL), which is coupled with a fractional- N injection-locked frequency divider (ILFD). The fractional- N injection-locking operation is achieved by the proposed self-synchronized gating injection technique. The principle of a fractional- N injection locking operation and the concept of the proposed circuits are described in detail. Analys is for predicting the locking range of the proposed fractional- N ILFD is investigated. A digital calibration scheme is adopted in order to compensate for proc ess, voltage, and temperature (PVT) variations. Implemente di na6 5n mC M O Sp r o c e s s ,t h i s work demonstrates continuous frequency coverage from 10 MHz to 6.6 GHz with quadrature phase output while occupying a s m a l la r e ao f0 . 3 8m m 2 and consuming 16 to 26 mW, depending on the output frequency. The normalized phase noise achieves -135.3 dBc/Hz at an offset of 3 MHz and -95.1 dBc/Hz at a n offset of 10 kHz, both from a carrier frequency of 1.7 GHz.