Current-Mode Transceiver for Silicon Interposer Channel Seung-Hun Lee, Seon-Kyoo Lee, Byungsub Kim, Hong-June Park, and Jae-Y

Abstract

An energy-ef ficient 3 Gb/s current-mode interface scheme is proposed for on-chip global interconnects and sil- icon interposer channels. The tr ansceiver core consists of an open-drain transmitter with one -tap pre-emphasis and a current sense ampli fier load as the receiver. The current sense ampli fier load is formed by stacking a PMOS diode stage and a cross-cou- pled NMOS stage, providing an optimum current-mode receiver without any bias current. The proposed scheme is veri fied with two cases of transceivers implemented in 65 nm CMOS. A 10 mm point-to-point data-only channel shows an energy ef ficiency of 9.5 fJ/b/mm, and a 20 mm four-drop source-synchronous link achieves 29.4 fJ/b/mm including clock and data channels.