Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails Inyong Kwon, Student Member , IEEE, Seongjong Kim

Abstract

This paper presents Razor-Lite, which is a low-over- head register for use in error detection and correction (EDAC) systems. These systems are able to eliminate timin g margins by using specialized registers to detect setup time violations. However, these EDAC registers incur signi ficant area and energy overheads, which mitigates some the system bene fits. R azor-Lite is a new EDAC register that addresses this issue by adding only 8 addi- tional transistors to a conventional flip-flop design. The Razor-Lite flip-flop achieves low overhead via a char ge-sharing technique that attaches to a standard flip-flop without modifying its design. Side-channels connected to the floating nodes generate error flags through simple logic gates to taling 8 transistors, enabling register energy/area overheads of 2.7%/33% over a conventional DFF, while also not incurring extra clock or datapath loading or delay. Razor-Lite is demonstra ted in a 7-stage Alpha architecture processor in a 45nm SOI CMOS technology with a measured energy improvement of 83% while incurring a 4.4% core area overhead compared to a baseli ne design.