A 5 Gb/s, 10 ns Power-On-Time, 36 W Off-State Power, Fast Power-On Transmitter for Energy Proportional Links Tejasvi Anand, Student Member , IEEE

Abstract

A fast power-on transmitter architecture that enables energy proportional co mmunication for server and mobile plat- forms is presented. The proposed architecture and circuit tech- niques achieve fast power-on capability in voltage mode output driver by using fast-digital regulator , an d in the clock multiplier by accurate frequency pre-setting and periodic reference insertion. To ease timing requirements, an improved edge replacement logic circuit for the clock multiplier is pr oposed. The proposed trans- mitter demonstrates energy proportional operation over wide vari- ations of link utilization, and is therefore suitable for energy ef fi- cient links. Fabricated in 90 nm CMOS technology, the voltage mode driver and the clock multiplier achieve power-on-time of only 2 ns and 10 ns, respectively. By using highly scalable digital architecture with accurate frequency pre -setting and instantaneous phase acquisi- tion, the prototype MDLL-based clock multiplier achieves 10 ns (3 reference cycles) power-on- time, 2 ps long-term absolute jitter at 2.5 GHz output frequency. Th e proposed fast power-on trans- mitter architecture consumes 4.8 mW/36 W on/off-state power from 1.1 V supply, has 10 ns t otal power-on time, and achieves 100 effective data rate scaling (5 Gb/s-0.048 Gb/s), while scaling the power and energy ef ficiency by only 50 (4.8 mW–0.095 mW) and 2 (1–2 pJ/Bit), res pectively. The proposed transmitter occu- pies an active die area of 0.3 mm .